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PRELIMINARY
MX53L03200
ROM MultiMediaCard
1.General Description
The MultiMediaCard MX53L03200 is a highly integrated read only memory (ROM) with serial and random access capability using an innovative ultra high density cell design in the memory array. It is accessible via a dedicated serial interface optimized for fast and reliable data transmis-sion. This interface allows several cards to be stacked by through connecting their peripheral contacts. The MX53L03200 is fully compatible to a new consumer standard, called the MultiMediaCard system standard defined in the MultiMediaCard system specification [1]. The MultiMediaCard system is a new mass-storage system based on innovations in semiconductor technology. It has been developed to provide an inexpensive, mechanically robust storage medium in card form for multimedia consumer applications. MultiMediaCard allows the design of inexpensive players and drives without moving parts. A low power consumption and a wide supply voltage range favors mobile, battery-powered applications such as audio players, organizers, palmtops, electronic books, encyclopedia and dictionaries. Using very effective data compression schemes such as MPEG, the MultiMediaCard will deliver enough capacity for all kinds of multimedia data: software/programs, text, music, speech, images, video etc.
2. FEATURES
* 32 MByte memory capacity - Payload: 33,554,432 Bytes * Small card-sized package: 24x32x1.4 mm (WxLxH) * MultiMediaCard system standard compatibility - Sequential and block read supported (Command classes 0, 1 and 2) - Block size free programmable between 1 and 2048 bytes per block - Multiple block mode supported - CRC protected data communication - 2.0V to 3.6V operation voltage range of communication - 2.7V to 3.6V operation voltage range of memory access - Damage free powered card insertion and removal - Only MMC mode available * High speed serial interface with random access in block or serial mode - Byte addressable memory - up to 10 stacked card @ 5MHz @ 2.7-3.6V - up to 10 stacked card @ 20MHz @ 2.7-3.6V - up to 30 stacked card @ 5MHz @ 2.7-3.6V - Access time < 60 us @ 5MHz @ 2.7-3.6V - Access time < 15 us @ 20MHz @ 2.7-3.6V, random byte access * Low power dissipation - High speed: < 126 mW @ 20MHz @ 2.7V - Low power: < 13.5 mW @ 100kHz@ 2.7V - Power save: < 0.54 mW@ 0Hz @ 2.7V (in stby state)
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3.OVERVIEW
The following diagram shows an overview of the MX53L03200 internal architecture:
1
2
3
4
5
6
7
not connected CMD
VDD CLK Interface driver DAT
CMD
CLK
DAT
VDD
CID[127:0] RCA[15:0] CSD[127:0]
reset
Memory core interface
reset
Memory core
Figure 1 : MX53L03200 architecture All controllers in the MX53L03200 are clocked by the interface signal CLK. The card is controlled by the three line MultiMediaCard interface containing the signals: CMD, CLK, DAT (see "Chapter 4: Inter-face" for more details). For the identification of the MX53L03200 in a stack of MultiMediaCards a card identification register (CID) and a relative card address register (RCA) is foreseen. An additional register contains different types of operation parameters. This register is called card specific data register (CSD). The communication using the MultiMediaCard lines to access either the memory field or the registers is defined by the MultiMediaCard standard (see "Chapter 6: Communication"). The card has its own power on detection unit. No additional master reset signal is required to setup the card after power on. It is protected against shortcut during insertion and removal while the Multi-MediaCard system is powered up (see "Chapter 9: Power supply").
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4. INTERFACE
In the MX53L03200 all data is transferred over a minimal number of lines: * CLK: with each cycle of this signal a one bit transfer on the command and data lines is done. The frequency may vary between zero and the maximum clock frequency. The MultiMediaCard bus master is free to generate these cycles without restrictions in the range of 0-20MHz. * CMD: is a bidirectional command channel used for card initialization and data transfer commands. The CMD signal has two operation modes: open drain for initialization mode and push pull for fast command transfer. Commands are sent from the MultiMediaCard bus master to the MX53L03200 and responses vice versa. * DAT: is a data channel with a width of one line. The DAT signal of the MX53L03200 operates in push pull mode.
ROD
RDAT
RCMD
Interface driver
CMD DAT CLK
MultiMediaCard Host
1 234567 MX53L03200
Figure 2: MX53L03200 interface
All MultiMediaCards are connected directly to the lines of the MultiMediaCard bus. The following table defines the card contacts. Pin No. 1 2 3 4 5 6 7 Name NC CMD VSS1 VDD CLK VSS2 DAT Type 1 -I/PP/OD S S I S PP Description not connected Command/Response Supply voltage ground Supply voltage Clock Supply voltage ground Data output
Table 1: MX53L03200 pad definition
1
S: power supply; I: input; PP: push pull output; OD: open drain output
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Pin 1 is not connected in the MX53L03200
7
DAT VSS2 CLK
MultiMediaCard interface controller
6
4
VDD
VSS1 CMD bus-mode enable Interface driver
1
2
Figure 3: MX53L03200 I/O-drivers
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5
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5 Registers
The MX53L03200 has the following information registers: Name CID RCA CSD Width 128 16 128 Type Mask programmable, read only for user Programmed during initialization, not readable Read only Description Card identification number, card individual number for identification. Relative card address, local system address of a card, dynamically assigned by the host during initialization. Card specific data, information about the card operation conditions.
Table 2: MX53L03200 registers CID and RCA are used for identifying and addressing the MX53L03200. The third register contains the card specific data record. This record is a set of information fields to define the operation conditions of the MX53L03200. For the user the CID and the CSD are read only registers. They are read out by special commands (see "Chapter 6.1: Commands"). The RCA register is a write only register. Unlike CID and CSD, RCA looses its contents after powering down the card. Its value is reassigned in each initialization cycle. The complete CID and parts of the CSD are programmed by the content provider via the programming mask (see "chapter 8: Programming mask format").
5.1 Card identification (CID) The Card IDentification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase (MultiMediaCard protocol). Every individual flash or I/O card shall have an unique identification number. Every type of MultiMediaCard ROM cards (defined by content) shall have an unique identification number. The structure of the CID register is defined in the following paragraphs: Name Manufacturer ID OEM/Application ID Product name Product revision Product serial number Manufacturing date CRC7 checksum not used, always '1'' Field MID OID PNM PRV PSN MDT CRC Width 8 16 48 8 32 8 7 1 CID-slice [127:120] [119:104] [103:56] [55:48] [47:16] [15:8] [7:1] [0:0] Value 0x07 "ROM032" 0x00CXXXXX
Table 3: The CID fields
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* MID An 8 bit binary number that identifies the card manufacturer. The MID number is controlled, defined and allocated to a MultiMediaCard manufacturer by the MMCA. This procedure is established to ensure uniqueness of the CID register. * OID A 16 bit binary number that identifies the card OEM and/or the card contents (when used as a distri-bution media either on ROM or FLASH cards). The OID number is controlled, defined and allocated to a MultiMediaCard manufacturer by the MMCA. This procedure is established to ensure uniqueness of the CID register. * PNM The product name is a string, 6 ASCII characters long. * PRV The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, repre-senting an "n.m" revision number. The "n" is the most significant nibble and "m" is the least significant nibble. As an example, the PRV binary value field for product revision "6.2" will be: 0110 0010 * PSN A 32 bits unsigned binary integer. * MDT The manufacturing date is composed of two hexadecimal digits, four bits each, representing a two digits date code m/y; The "m" field, most significant nibble, is the month code. 1 = January. The "y" field, least significant nibble, is the year code. 0 = 1997. As an example, the binary value of the MDT field for production date "April 2000" will be: 0100 0011. * CRC CRC7 checksum (7 bits). This is the checksum of the CID contents.
The CID has to be error free. To ensure the correctness of the CID a CRC checksum is added to the end of the CID. The CRC checksum is computed by the following formula: CRC Calculation: G(x) = x 7 + x 3 + 1 M(x) = CID[127]*x 119 +...+ CID[8]*x 0 CRC[6...0] = Remainder [(M(x)*x 7)/G(x)] In the MX53L6401 the CID is programmed with parameters defined by the content provider. The programming is done by the mask which is used for the data programming too. Details of the mask programming and the formats of data transfer between content provider and card manufacturer are defined in "Chapter 8: Programming mask format".
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5.2 Relative card address (RCA) The 16-bit relative card address register carries the card address assigned by the host during the card identification. This address is used for the addressed host to card communication after the card identification procedure. The default value of the RCA register is 0x0001. The value 0x0000 is reserved to set all cards in Standby State with the command SELECT_DESELECT_CARD (CMD7). The RCA is programmed with the command SET_RELATIVE_ADDRESS (CMD3) during the initialization procedure. The content of this register is lost after power down. The default value is assigned when an internal reset is applied by the power up detection unit of the MX53L03200.
5.3 Card specific data (CSD) The card specific data register describes how to access the card content. The CSD defines the data format, error correction type, maximum data access time, data transfer speed, whether the wide or standard bus is implemented etc. CSD-slice [127:126] [125:122] [121:120] [119:112] [111:104] [103:96] [95:84] [83:80] [79:79] [78:78] [77:77] [76:76] [75:74] [73:62] [61:59] [58:56] [55:53] [52:50] [49:47] [46:42] [41:37] [36:32] [31:31] [30:29] [28:26] Width 2 4 2 8 8 8 12 4 1 1 1 1 2 12 3 3 3 3 3 5 5 5 1 2 3 Value 1 1 don't care 0x08(1ns) 0x03(300 cycles) 0x2A(20 Mbit/s) 0x007 (class 0,1,2) 0xB (2048 bytes) "1" don't care "1" "0" don't care 0xFFF 0x4(25mA) 0x4(35mA) don't care don't care 0 don't care don't care don't care don't care don't care don't care Field CSD_STRUCTURE MMC_PROT _ TAAC NSAC TRAN_SPEED CCC READ_BLK_LEN READ_BLK_PARTIAL WRITE_BLK_MISALIGN READ_BLK_MISALIGN DSR_IMP C_SIZE VDD_R_CURR_MIN VDD_R_CURR_MAX VDD_W_CURR_MIN VDD_W_CURR_MAX C_SIZE_MULT SECTOR_SIZE ERASE_GRP_SIZE WP_GRP_SIZE WP_GRP_ENABLE DEFAULT_ECC R2W_FACTOR
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CSD-slice [25:22] [21:21] [20:16] [15:15] [14:14] [13:13] [12:12] [11:10] [9:8] [7:1] [0:0]
Width 4 1 5 1 1 1 1 2 2 7 1
Value don't care don't care don't care don't care don't care 1 1 don't care 0 CRC value 1
Field WRITE_BLK_LEN WRITE_BLK_PARTIAL COPY PERM_WRITE_PROTECT TMP_WRITE_PROTECT ECC CRC -
All CSD fields are read only for the user. All don't care tagged field are zero. The following section describles the CSD fields and their values for the MX53L03200: CSD_STRUCTURE The CSD version of the MX53L03200 is related to the CSD version 1.1 as defined in "MultiMediaCard system specification, Version 1.4". The parameter CSD_STRUCTURE is permanently assigned to the value 1.
MMC_PROT Defines the MultiMediaCard protocol version supported by the card. It includes the commands set definition and the definition of the card responses. The card identification procedure is compatible for all protocol versions. The MultiMediaCard protocol version of the MX53L03200 is related to the"MultiMediaCard system specification, Version 1.4". The parameter MMC_PROT is permanently assigned to the value 1.
TAAC Defines the asynchronous data access time: TAAC bit Description Values 2:0 time unit 0=1ns, 1=10ns, 2=100ns, 3=1ms, 4=10ms, 5=100ms, 6=1ms, 7=10ms 6:3 time value 0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5, 5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5, B=5.0, C=5.5, D=6.0, E=7.0, F=8.0 7 reserved always "0" Table 5: TAAC access time definition The coded TAAC value is 0x08. For more details see "Chapter 10.2.4: Operating characteristics".
NSAC Defines the worst case for the synchronous data access time. N AC is defined as 100*NSAC clock cycles, where NSAC represents a binary value. Max. value for the data access time N AC is 25.6k clock cycles. The total access time is the sum of both TAAC and N AC * clock period. The value of NSAC for the MX53L03200 is 0x03 (300 cycles). For more details see "Chapter 10.2.4: Operating characteristics".
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TRAN_SPEED The following table defines the maximum data transfer rate TRAN_SPEED: TRAN_SPEED bit Description 2:0 transfer rate unit 0=100kbit/s, 1=1Mbit/s, 2=10Mbit/s, 3=100Mbit/s, 4... 7=reserved 6:3 time value 0x0=reserved, 0x1=1.0, 0x2=1.2, 0x3=1.3, 0x4=1.5, 0x5=2.0, 0x6=2.5, 0x7=3.0, 0x8=3.5, 0x9=4.0, 0xA=4.5, 0xB=5.0, 0xC=5.5, 0xD=6.0, 0xE=7.0, 0xF=8.0 7 reserved="0" Table 6: Maximum data transfer rate definition The MX53L03200 supports a transfer rate between 0 and 20 Mbit/s.The parameter TRAN_SPEED is 0x2A. CCC The MultiMediaCard command set is divided into subsets (command classes). The card command class register CCC defines which command classes are supported by this card. A set CCC bit means that the corresponding command class is supported. For command class definition refer to Table 13. CCC bit Supported card command class 0 class 0 1 class 1 ...... 11 class 11 Table 7: Supported card command classes The MX53L03200 supports the command classes 0, 1 and 2.The parameter CCC is permanently assigned to the value 0x007. READ_BLK_LEN The data block length can be computed as 2 READ_BLK_LEN . The block length might therefore be in the range 1, 2,4...2048 bytes. READ_BLK_LEN Block length Remark 0 0 2 = 1 byte 1 2 1 = 2 byte ...... 11 2 11 = 2048 byte 12-15 reserved Table 8: Data block length coding
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READ_BLK_PARTIAL READ_BLK_PARTIAL defines whether partial block sizes can be used in block read. READ_BLK_PARTIAL=0 means that only the READ_BLK_LEN block sizes can be used for block oriented data transfers. READ_BLK_PARTIAL=1 means that smaller blocks can be used as well. The minimum block size will be equal to minimum addressable unit (one byte). The MX53L03200 supports partial block read. The parameter READ_BLK_PARTIAL is permanently assigned to the value `1'. READ_BLK_MISALIGN Defines if the data block to be read by one command can be spread over more than one physical block of the memory device. The size of the data block is defined in READ_BLK_LEN. READ_BLK_MISALIGN=0 signals that crossing physical block boundaries is not allowed. READ_BLK_MISALIGN=1 signals that crossing physical block boundaries is allowed. The MX53L03200 supports read block operations with boundary crossing. The parameter READ_BLK_MISALIGN is permanently assigned to the value "1".
DSR_IMP Defines if the configurable driver stage option is integrated on the card or not. If implemented a driver stage register (DSR) must be implemented also. DSR_IMP DSR type 0 no DSR implemented 1 DSR implemented Table 9: DSR implementation The MX53L03200 output drivers are not configurable. The parameter DSR_IMP is permanently assigned to the value"0". C_SIZE, C_SIZE_MULT This parameter is used to compute the card capacity. The memory capacity of the card is computed from the entries C_SIZE, C_SIZE_MULT and READ_BLK_LEN as follows: BLOCKLEN = 2 READBLKLEN = 2048 (READBLKLEN < 12) MULT = 2 CSIZEMULT +2 = 4 (CSIZEMULT< 8) BLOCKNR = (CSIZE+1) * MULT = 3852 SIZE = BLOCKNR * BLOCKLEN = 7,888,896 Byte The memory size of the MX53L03200 is 32MByte. The parameter C_SIZE is 0xFFF, the parameter C_SIZE_MULT is 0 and the parameter READ_BLK_LEN is 0xB (see above).
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VDD_R_CURR_MIN The maximum supply current at the minimal supply voltage V DD (2.7V): VDD_R_CURR_MIN[2:0] 0=0.5 mA; 1=1 mA; 2=5 mA; 3=10 mA; 4=25 mA; 5=35 mA; 6=60 mA; 7=100 mA
Table 10: Supply current consumption @ V DD =2.7V The parameter VDD_R_CURR_MIN is permanently assigned to the value 4 (25 mA).
VDD_R_CURR_MAX The maximum supply current at the maximum supply voltage V DD (3.6V): VDD_R_CURR_MAX[2:0] 0=1 mA; 1=5 mA; 2=10 mA; 3=25 mA; 4=35 mA; 5=45 mA; 6=80 mA; 7=200 mA
Table 11: Supply current consumption @ V DD =3.6V The parameter VDD_R_CURR_MAX is permanently assigned to the value 4 (35 mA).
PERM_WRITE_PROTECT Permanently protects the whole card content against overwriting or erasing (all write and erase commands for this card are permanently disabled). This parameter has permanently the value "1".
TMP_WRITE_PROTECT Temporarily protects the whole card content from being overwritten or erased (all write and erase commands for this card are permanently disabled). This parameter has always the value "1".
ECC Defines the ECC code that was used for storing data on the card. This field is used by the host (or application) to decode the user data.The following table defines the field format. ECC 0 1 2-15 ECC type none (default) BCH (542,512) reserved Maximum number of correctable bits none 3 Table 12: ECC type No external error correction is needed for the MX53L03200. The parameter ECC is permanently assigned to the value 0.
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CRC The CRC register carries the check sum for the CSD content. The check sum is computed by the following formulas: Generator polynomial: G(x) = x 7 + x 3 + 1 M(x) = CSD[127] * x 119 + ... + CSD[8] * x 0 CRC[6...0] = Remainder [(M(x)* x 7 ) / G(x).
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6 Communication
All communication between host and cards is controlled by the host (master). The host sends com-mands and, depending on the command, receives a corresponding response from the selected card. In this chapter the commands to control the MX53L03200, the card responses and the contents of a status and error field, included in the responses, are defined.
6.1 Commands The command set of the MultiMediaCard system is divided into classes corresponding to the type of card (see also [1]). The MX53L03200 supports the following command classes: Card Command Class (CCC) class 0 class 1 class 2 Class description basic sequential read block read
Supported commands 012 3 47 +++ + + +
9 +
10 +
11 +
12 +
13 +
15 +
16
17
18
+ Table 13: MX53L03200 command classes
+
+
Class 0 is mandatory and supported by all cards. It represents the card identification and initialization commands, which are intended to handle different cards and card types on the same bus lines. The Card Command Class (CCC) is coded in the card specific data register of each card, so that the host knows how to access the card. There are four kinds of commands defined on the MultiMediaCard bus: * broadcast commands (bc) sent on CMD line, no response * broadcast commands with response (bcr) sent on CMD line, response (all cards simultaneously) on CMD line * addressed (point-to-point) commands (ac) sent on CMD line, response on CMD line * addressed (point-to-point) data transfer commands (adtc) sent on CMD line, response on CMD line, data transfer on DAT line The command transmission always starts with the MSB. Each command starts with a start bit and ends with an CRC command protection field followed by a end bit. The length of each command frame is fixed to 48 bits (2.4 ms @ 20 MHz): 0 start bit
1
1 host
bit 5...bit 0 command
bit 31...bit 0 argument
bit 6...bit 0 CRC 1
1 end bit
Cyclic Redundancy Check
The start bit is always "0" in command frames (sent from host to MultiMediaCard). The host bit is always "1" for commands. The command field contains the binary coded command number. The argument depends on the command (see Table 14 and Table 15). The CRC field is defined in "Chapter 7: Error handling".
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The MX53L03200 supports the following MultiMediaCard command: CMD Type Argument INDEX CMD0 bc [31:0] stuff bits CMD1 bcr argument ignored Resp R3 Abbreviation Command Description
CMD2 CMD3 CMD4 CMD7
bcr ac bc ac
[31:0] stuff bits [31:16] RCA [15:0] stuff bits [31:16] DSR [15:0] stuff bits [31:16] RCA [15:0] stuff bits
R2 R1 R1 (only the selected card)
GO_IDLE_STATE resets all cards to Idle State SEND_OP_COND checks for cards not supporting the full range of 2.0 to 3.6V. After receiving CMD1 the card sends an R3 response (see "Chapter 6.5: Responses"). ALL_SEND_CID asks all cards in ready state to send their CID 1 numbers on CMD-line SET_RELATIVE_ assigns relative address to the card ADDR in identification state. SET_DSR programs the DSR of all cards in stand-by state. SELECT_ DESELECT_ CARD command toggles a card between the standby and transfer states or between the programming and disconnect state. In both cases the card is selected by its own relative address while deselecting the prior selected card. Address 0 deselects all. asks the addressed card to send its cardspecific data (CSD)2 on CMD-line. asks the addressed card to send its card identification (CID) on CMD-line. reads data stream from the card in sendingdata state, starting at the supplied address, until STOP_TRANSMISSION follows. forces the card to stop transmission Asks the addressed card to send its status register. Sets the card to inactive state in order to protect the card stack against communications breakdowns.
CMD9
ac
CMD10 ac CMD11 adtc
[31:16] RCA [15:0] stuff bits [31:16] RCA [15:0] stuff bits [31:0] data
R2 R2 R1
SEND_CSD SEND_CID READ_DAT_ UNTIL_STOP STOP_ TRANSMISSION SEND_STATUS GO_INACTIVE_ STATE
CMD12 ac CMD13 ac CMD15 ac
[31:0] stuff bits [31:16] RCA [15:0] stuff bits [31:16] RCA [15:0] stuff bits
R1 R1 -
Table 14: Basic commands for read only devices (class 0 and class 1) 1.CID register consists of 128 bits (starting with MSB, it is preceded by an additional start bit, ends with an end bit) 2.CSD register consists of 128 bits (starting with MSB, it is preceded by an additional start bit, ends with an end bit) 3.The addressing capability @ 8 bit address resolution is 2 32 = 4 Gbyte
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CMD INDEX
Type Argument [31:0] block length
Resp R1 R1 R1
Abbreviation SET_BLOCKLEN READ_SINGLE_ BLOCK BLOCK
Command Description Selects a block length (in bytes) for all following block commands (read and write).1 Reads a block of the size selected by the SET_BLOCKLEN command.2 interrupted by a stop command.
CMD16 ac
CMD17 adtc [31:0] data address CMD18 adtc [31:0] data address
READ_MULTIPLE_ Continuously send blocks of data until
Table 15: Block oriented read commands (class 2) 1.The default block length is as specified in the CSD. 2.The data transferred must not cross a physical block boundary unless RD_BLK_MISALIGN is set in the CSD.
6.2 Card identification mode All the data communication in the card identification mode uses only the command line (CMD).
Power on
Idle State (idle)
CMD0
from all states except (ina)
CMD1
Inactive State (ina)
CMD15
Ready State (ready) Card looses bus
CMD2 Card wins bus Identification State (iden)
CMD3
card-identification
Stand-by State (stby)
data-transfer mode
from all states in data-transfer-mode
Figure 4: MultiMediaCard state diagram (card identification mode)
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The host starts the card identification process in open drain mode with the identification clock rate f OD (generated by a push pull driver stage). The open drain driver stages on the CMD line allow the parallel card operation during card identification. After the bus is activated the host will request the cards to send their valid operation conditions with the command SEND_OP_COND(CMD1). Since the bus is in open drain mode, as long as there is more than one card with operating conditions restrictions, the host gets in the response to the CMD1 a "Wired or" operation condition restrictions of those cards. The host then must pick a common denominator for operation and notify the application that cards with out of range parameters (from the host perspective) are connected to the bus. Incompatible cards go into Inactive State. After an operating mode is established, the host asks all cards for their unique card identification (CID) number with the broadcast command ALL_SEND_CID (CMD2). All not already identified cards (i.e. those which are in Ready State) simultaneously start sending their CID numbers serially, while bit-wise monitoring their outgoing bit stream. Those cards, whose outgoing CID bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). There should be only one card which successfully sends its full CID-number to the host. This card then goes into the Identification State. The host assigns to this card (using CMD3, SET_RELATIVE_ADDR) a relative card address (RCA, shorter than CID), which will be used to address the card in future communication (faster than with the CID). Once the RCA is received the card transfers to the Standby State and does not react to further identification cycles. The card also switches the output drivers from the open-drain to the push-pull mode in this state. The host repeats the identification process as long as it receives a response (CID) to its identifica-tion command (CMD2). When no card responds to this command, all cards have been identified. The time-out condition to recognize this, is waiting for the start bit for more than 5 clock periods after sending CMD2.
6.3 Operating voltage range validation The MultiMediaCard standards operating range validation is intended to support reduced voltage range MultiMediaCards. The MX53L03200 supports the full range of 2.5 to 3.6V supply voltage. So the MX53L03200 sends a R3 response to CMD1 which contains an OCR value of 0x00FFE000 (see "Chapter 6.5: Responses").
6.4 Data transfer mode When in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all CSD registers is not known, the f PushPull clock rate is equal to the slow f OpenDrain clock rate. SEND_CSD (CMD9) allows the host to get the Card Specific Data (CSD register), e.g. ECC type, block length, card storage capacity, maximum clock rate etc.
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card identification mode CMD3 CMD15 CMD0
from all states in data-transfer-mode data transfer mode
Sending-data State
CMD13 no state transition in data-transfer-mode
CMD7 card is not addressed Stand-by State (stby)
CMD12 "operation complete"
CMD11, 17, 18
CMD7 card is addressed
Transfer State(tran)
CMD16
CMD4, 9,10
Figure 5: MX53L03200 state diagram (data transfer mode)
The command SELECT_DESELECT_CARD (CMD7) is used to select one card and place it in the Transfer State. If a previously selected card is in the Transfer State its connection with the host is released and it will move back to the Stand-by State. Only one card can be, at any time, in the Transfer State. A selected card is responding the CMD7, the deselected one does not respond to this command. When CMD7 is sent including the reserved relative card address "0x0000", all cards transfer back to Stand-by State. This command is used to identify new cards without resetting other already acquired cards. Cards to which an RCA has already been assigned, do not respond to the identification command flow in this state. All the data communication in the Data Transfer Mode is consequently a point-to point communication between the host and the selected card (using addressed commands). All addressed commands are acknowledged by a response on the CMD line. All read commands (data is sent from the card via data lines) can be interrupted at any time, by another read or a stop command. The DAT bus line is high when no data is transmitted. A transmitted data block consists of a start bit (LOW), followed by a continuous data stream. The data stream contains the net payload data (and error correction bits if an off-card ECC is used). The data stream ends with an end bit (HIGH). The data transmission is synchronous to the clock signal. The payload for block oriented data transfer is protected by a CRC check sum (see "Chapter 7:Error handling").
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Stream read There is a stream oriented data transfer controlled by READ_DAT_UNTIL_STOP (CMD11). This command instructs the card to send its payload, starting at a specified address, until the host sends a STOP_TRANSMISSION command (CMD12). Please note that the host stop command has an execution delay due to the serial command transmission. The data transfer stops after the end bit of the next command with interrupt ability. If the end of the memory range is reached while sending data and no stop command has yet been sent by the host, the data transfer will continued. The data sent than is undefined. The host has to observe the boundaries of the memory range.
Block read Block read is similar to stream read, except the basic unit of data transfer is a block whose maxi-mum size is defined in the CSD (READ_BLK_LEN). READ_BLK_PARTIAL is set, thus smaller blocks whose starting and ending address are wholly contained within one physical block (as defined by READ_BLK_LEN) may also be transmitted. Unlike stream read, a CRC is appended to the end of each block ensuring data transfer integrity. READ_SINGLE_BLOCK (CMD17) starts a block read and after a complete transfer the card goes back to Transfer State. READ_MULTIPLE_BLOCK (CMD18) starts a transfer of several consecutive blocks. Blocks will be continuously transferred until a stop command is issued. Block misalignment is also allowed for the MX53L03200 .
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State transition summary The Table 16 defines the card state transitions as a function of received command. current state ident stby idle stby idle stby tran stby stby stby ina -
CRC fail commands of not supported classes class 0 CMD0 CMD1 CMD2,card wins bus CMD2,card loses bus CMD3 CMD4 CMD7,card is addressed CMD7,card is not addressed CMD9 CMD10 CMD12 CMD13 CMD15 class 1 CMD11 class 2 CMD16 CMD17 CMD18
idle -1 idle ready -
ready idle ident ready -
tran idle stby tran ina data tran data data
data idle stby tran data ina -
ina -
-
Table 16: Card state transition table
1
Stay in the current state.
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6.5 Responses All responses are sent via command line (CMD), all data starts with the MSB. Format R1 (response command): response length 48 bit. 0 start bit 0 card bit 5...bit 0 command bit 31...bit 0 status bit 6...bit 0 CRC 1 end bit
The contents of the status field are described in "Chapter 6.6: Status" Format R2 (CID, CSD register): response length 136 bits. Note: Bit 127 down to bit 1 of CID and CSD are transferred, the reserved bit [0] is replaced by the end bit. 0 start bit 0 card bit 5...bit 0 reserved bit 127...bit 1 CID or CSD register including internal CRC 1 end bit
CID register is sent as a response to commands CMD2 and CMD10. CSD register is sent as a response to the CMD9.
Format R3 (OCR): response length 48 bits. 0 start bit 0 card bit 5...bit 0 reserved bit 31...bit 0 OCR field bit 6...bit 0 reserved 1 end bit
The OCR is sent as a response to the CMD1 to signalize the supported voltage range. The MX53L03200 supports the full range from 2.5 to 3.6 V. Respectively the value of all bits of the OCR field of the MX53L03200 are always set to high (0x00FFE000). The reserved bits are also high (0x3F and 0x7F). So the R3 frame of the MX53L03200 contains always the value 0x3F00FFE000FF.
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6.6 Status The response format R1 contains a 32-bit field with the name card status. This field is intended to transmit status information which is stored in a local status register of each card to the host. The fol-lowing table defines the status register structure. The Type and Clear-Condition fields in the table are coded as follows: * Type: - E-Error bit. - S-Status bit. - R-Detected and set for the actual command response. - X-Detected and set during command execution. The host must poll the card by sending status command in order to read these bits. * Clear Condition: - A- According to the card state. - B- Always related to the previous command. Reception of a valid command will clear it (with a delay of one command). - C- Clear by read.
Bits 31 30 29 Identifier Don't care Don't care BLOCK_LEN_ERROR ER '0 Type Value Permanently 0 Permanently 0. "0"=no error "1"=error 28:26 25:24 23 22 21 20 19 18 17:13 12:9 Don't care reserved COM_CRC_ERROR ILLEGAL_COMMAND Don't care Don't care Don't care Don't care Don't care CURRENT_STATE SX ER '0 ER '0 Permanently 0. Permanently 0. "0"=no error "1"=error "0"=no error Permanently 0. Permanently 0 Permanently 0. Permanently 0 Permanently 0. 0 = idle 1 = ready 2 = ident 3 = stby 4 = tran 5 = data 8 7:0 Don't care reserved 6-15 = reserved Permanently 0. Permanently 0. Current state of the card. Current state of the card. B B The CRC check of the previous command failed. Command not legal for the current state. B B The transferred block length is not allowed for this card or the number of bytes transferred does not match the block length. C Description Clear Condition
Table 17: Status
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6.7 Command and response timings All timing diagrams use the following schematics and abbreviations: S T P E Z D * CRC Start bit (= 0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (= 1) End bit (=1) high impedance state (-> = 1) Data bits repeater Cyclic redundancy check bits (7 bits) Card active Host active
Table 18: Timing diagram symbols
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card respectively host output driver, while the Z-bit is driven to (respectively kept) HIGH by the pull-up resistors R CMD respectively R DAT . Activelydriven P-bits are less sensitive to noise superposition. For the timing of the MX53L03200 the following values are defined: Value [clock cycles] 5 5 TAAC+NSAC 8 >8 >8 Description Number of cycles between command and response Number of cycles between card identification or card operation conditions com-mand and the correspond-ing response. Number of cycles between blocks in multiple block read Number of cycles between two commands, if no response will be sent after the first command (e.g.broadcast) Table 19: Timing values
N CR N ID N AC N BAC N RC N CC
The host command and the card response are clocked out with the rising edge of the host clock.The delay between host command and card response is N CR clock cycles. The following timing diagram is relevant for host command CMD3:
Host command NCR cycles Response
CMD
S
T
content
CRC
E
Z
******
Z
S
T
content
CRC
E
Z
Z
Z
Figure 6: Command response timing (identification mode)
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There is a two Z bit period followed by P bits pushed up by the responding card. The following tim-ing diagram is relevant for all host commands followed by a response, except CMD1, CMD2 and CMD3:
Host command NCR cycles Response
CMD
S
T
content
CRC
E
Z
Z
P
***
P
S
T
content
CRC
E
Z
Z
Z
Figure 7: Command response timing (data transfer mode)
Card identification and card operation conditions timing The card identification (CMD2) and card operation conditions (CMD1) timing are processed in the open-drain mode. The card response to the host command starts after exactly NID clock cycles.
Host command NID cycles CID or OCR Z S T content Z Z Z
CMD
S
T
content
CRC
E
Z
******
Figure 8: Identification timing (card identification mode)
Last card response - next host command timing After receiving the last card response, the host can start the next command transmission after at least N RC clock cycles. This timing is relevant for any host command.
Response NRC cycles Host command
CMD
S
T
content
CRC
E
Z
******
Z
S
T
content
CRC
E
Figure 9: Timing response end to next CMD start (data transfer mode)
Last host command - next host command timing diagram After the last command, which does not force a response, has been sent, the host can continue sending the next command after at least N CC clock periods.
Host command NCC cycles Response
CMD
S
T
content
CRC
E
Z
******
Z
S
T
content
CRC
E
Figure 10: Timing CMD n end to CMD n+1 start (all modes) In the case the CMD n command was a last identification command (no more response sent by a card), then the next CMD n+1 command is allowed to follow after at least N CC +136 (the length of the R2 response) clock periods.
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Data access timing Data transmission starts with the access time delay t AC (which corresponds to N AC ), beginning from the end bit of the data address command. The data transfer stops automatically in case of a data block transfer or by a transfer stop command.
Host command NCR cycles Response
CMD
S
T
content
CRC
E
Z
Z
P
***
P
S
T
content
CRC
E
NAC cycles DAT Z Z Z Z Z Z Z Z Z P P
Read Data
****
************
S
D
D
D
***
Figure 11: Data read timing (data transfer mode) Data transfer stop command timing The card data transmission can be stopped using the stop command. The data transmission stops immediately with the end bit of the stop command.
Host command NCR cycles Response
CMD
S
T
content
CRC
E
Z
Z
P
***
P
S
T
content
CRC
E
DAT
D
D
D
********
D
D
D
E
Z
Z
********************
Figure 12: Timing of stop command (CMD12, data transfer mode)
Data transfer stop The read command (CMD11, 17, 18) is ignored, while data transmission is active. Only STOP command(CMD12) or DESELECT_CARD (CMD7) is able to stop the data transmission task.
Next data block transfer timing In multiple block read mode, the next data block transmission starts with the delay time tBAC(NBAC Clock cycles), beginning from the end bit of the previous data block.
tBAC
DAT D D D E P **** P S D D
Start bit of next data block
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6.8 Clock Control The bus frequency can be changed at any time (under the restrictions of masimum data trandfer frequency, defined by the cards, and the identification frequency defined by the specification document). It is an obvious requirement that the clock must be running for the card to output data or response tokens. After the last MultiMediaCard bus transaction, the host is required, to provide 8(eight) clock cycles for the card to complete the operation before shutting down the clock. Following is a list of the various bus transactions: * A command with no response. 8 clocks after the host command end bit. * A command with response. 8 clocks after the card response end it. * A read data transaction. 8 clocks after the end bit of the last data block.
6.9 Reset GO_IDLE_STATE(CMD0) is the software reset command, which sets the R0008 into the Idle State independently of the current state. In the Inactive State the R008 is not affected by this command. After power-on the MX53L03200 is always in the Idle State. After power-on or command the card will be initialized with a default relative card address ("0x0001"). The host runs at the identification clock rate fOD generated by a push-pull driver stage(see also "Chapter 8.2 Power On" for more details).
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7 Error handling
The MX53L03200 is defined as an error free device. To protect the data against errors generated during the transport over the MultiMediaCard bus dynamically, an additional feature is implemented: The cyclic redundancy check (CRC). 7.1 CRC Following the MultiMediaCard standard, the MX53L03200 uses two different CRC codes to protect the data and the command/response transfer between card and host. The CRC is intended only to detect transfer errors and not to correct them "on the fly". If a CRC error is detected the host has to react. This is normally done by repeating the last command. The first CRC code is intended to protect the command and response frames. They are also used to synchronize the data stream. This CRC is generated with and checked against the following polyno-mial: CRC polynomial: G(x) = x 7 + x 3 + 1 M(x) = (start bit) * x 39 +...+ (last bit) * x 0 CRC[6...0] = Remainder [(M(x) * x 7 ) / G(x)] One CRC is checked in the MX53L03200 for every command. For each response a CRC is generated in the MX53L03200. On CRC failure the command will be ignored and a response is sent to initiate a repeti-tion of the command by the host. Each data block read from the MX53L03200 will be succeeded by redun-dancy bits generated with the second CRC. The code is usable for payload lengths of up to 2048 Bytes: CRC polynomial: G(x) = x 16 + x 12 +x 5 + 1, M(x) = (start bit) * x n + x n-1 +...+ (last bit) * x 0 , with n < 2048*8 CRC[15...0] = Remainder [(M(x) * x 16 ) / G(x)]
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8 Power supply
8.1 Power supply decoupling The VSS1, VSS2 and VDD lines supply the card with operating voltage. A decoupling capacitor (C) for current peak buffering has to be foreseen. This capacitor is placed on the bus side corresponding to Figure 14.
Length max=13mm single card solt
VDD C VSS1 VSS2 Card
single card solt
Figure 14: Power supply decoupling
8.2 Power on Each card has its own power on detection circuitry which puts the card into a defined state after the power-on. No explicit reset signal is necessary. The cards can also be reset by a special software command: GO_IDLE_STATE (CMD0). In case of emergency the host may also reset the cards by switching the power supply off and on again.
CLK
CMD
DAT
VDD Power up detection ASYNC RESET Command parser ENABLE core controller memory core
VSS
MultiMediaCard controller
Figure 15: Power on detection
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A power-on-reset is generated on chip as long as V DD is below a certain value. After the power on reset the command parser of the MX53L03200 works properly, but the access to the memory core is not guaranteed as long as V DD min is not reached. Therefore in the power up phase (or when the MX53L03200 is inserted during power up) the host has to wait after sending the SEND_OP_COND command (CMD1) for the identification delay. After that the ALL_SEND_CID command(CMD2) can be interpreted by the card:
Supply voltage
VDD max [3.6]
Bus master supply voltage
Card logic working voltage range
Memory field working voltage range
VDD min [2.0V]
Power up time
Supply ramp up time
TIME
NCC Initlization sequence CMD1 CMD1
NCC CMD1
NCC CMD2
Identification delay: The maximum of 1 msec, 74 clock cycles and supply ramp up time
Optional repetitions of CMD1 until no cards are responding with busy bit set.
Figure 16: Power up diagram
For the MX53L03200 the following minimum initialization and identification delays are defined: Description Initialization delay Identification delay Symbol t init t ident Table 20: Initialization and identification delays Minimum Value @ f clk >64kHz @ f clk <64kHz 1 ms
1 ms 64 cycles
The initialization delay is relevant only after the system power up (>1 ms, at least 64 clock cycles). The identification delay is relevant for system power up and card hot insertion (> 1 ms). The MX53L03200 ignores all commands until the sequence CMD1, CMD2 is received and the RCA of the card is ini-tialized. The initialization delay guarantees enough time for V DD to reach the minimum operating voltage on the MultiMediaCard bus. The identification delay guarantees enough time for V DD to reach the minimum operating voltage internally in the MultiMediaCard.
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8.3 Power consumption The MX53L03200 power consumption depends on three parameters: * The operating frequency * The operating voltage * The card state In the following table the supply current and the power consumption of one MX53L03200 for typical operating conditions are listed. These parameters are typical values to give system designers some hints, all guaranteed parameters are listed in "Chapter 10.2: Electrical characteristics": Description Clock off Low speed Initialzation High speed Frequency 0 Hz 1 100kHz 400kHz2 20MHz Card state stby stby,tran idle, ready, ident, ina stby data, tran < 25mA < 35mA 2.7V < 100uA 3.6V < 200uA < 5mA < 5mA
Table 21: Typical MX53L03200 supply current values
1 2
Host has stopped generation of clock pulses. In the initialization phase. No access to the memory core.
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8.4 Short cut protection The MX53L03200 can be inserted/removed into/from the bus without damage. If one of the supply pins (VDD , VSS or VPP ) is not connected properly, then the current is drawn through a data line to supply the card. Naturally the card can not operate properly under these conditions.
VDD
VDD not connected CMD, DAT VSS not connected Card Control
VSS
Figure 17: Improper power supply
Every MX53L03200 output withstands shortcuts to either supply.
VDD I short
Worst case shortcut
CMD, DAT
Card Control I short
VSS
Figure 18: Short cut protection
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9 Characteristics
This chapter defines the following characteristics: * Temperature characteristics * Electrical characteristics * Mechanical characteristics
9.1 Temperature characteristics Parameter Storage Temperature Operating temperature
Symbol TSTG TA Table 22: Temperature characteristics
Min -40 -25
Max 85 85
Unit C C
9.2 Electrical characteristics In this chapter the electrical characteristics for the MX53L03200 are defined in three steps: * Pad characteristics: properties of the external connectors * Absolute maximum ratings: if exceeded the card may be damaged * Recommended operating conditions: characterization model of the environment of the MX53L03200, requirements for the operating characteristics * Operating characteristics: properties of the MX53L03200 measurable if the recommended operating conditions are considered 9.2.1 Pad characteristics Parameter Connector Resistance
Symbol
Min 10
Typ 30
Max 100
Unit m ohm
Counterpart is the MultiMediaCard connector defined in the MultiMediaCard system specification[1], Chapter 8, "Mechanical specification"
Input Capacitance
5
pF
Table 23: Pad characteristics
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9.2.2 Absolute maximum ratings Absolute maximum ratings are those values beyond which damage to the device may occur. Func-tional operation under these conditions or at any other condition beyond those indicated in the oper-ational sections of this specification is not implied: TA -20 ... 85 VDD 2 ... 3.6V unless otherwise stated C, Parameter supply voltage total power dissipation ESD protection latch-up protection inputs input voltage outputs output voltage high-level output current low-level output current Symbol V DD Min -0.5 -4 -100 V Imax -0.5V Max 4.6 0.9 4 100 VDD +0.5 Unit V W kV mA V V mA mA Remark
Human Body Model all inputs/outputs < VDDmax < VDDmax short cut protected short cut protected
V Omax -0.5V VDD +0.5 | I OH | 100 | I OL | 150 Table 24: Absolute Maximum Ratings
9.2.3 Recommended operating conditions The recommended operating conditions define the parameter ranges for optimal performance and durability of the MX53L03200. TA -20 ... 85 VDD 2 ... 3.6V unless otherwise stated C, Parameter Symbol Min Typ Max Unit Remark supply voltage V DD 2.0 3.6 V inputs low-level input voltage V IL VSS-0.3 0.25V DD V high-level input voltage V IH 0.625 VDD VDD+0.3 V outputs (push pull mode) high-level output current | I OH | 2 mA low-level output current | I OL | 2 mA clock input clk (all values are referred to min(V IH ) and max(V IL )) clock frequency data transfer mode(pp) f CLK 0 20 MHz <= 10 cards, CLmaxCMD,DAT = 100pF, Rpullup = 4.7k clock frequency data transfer mode(pp) f CLK 0 5 MHz <= 30 cards, CLmaxCMD,DAT = 250pF, Rpullup = 1.65k clock frequency ident. mode (od) f CLK 0 400 kHz <= 30 cards, CLmaxCMD,DAT = 250pF, Ropen drain = 1.65k clock low time tWL 10 ns S. Figure 20 clock high time tWH 10 ns S. Figure 20 Table 25. Recommended Operating Condition
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9.2.4 Operating characteristics The operating characteristics are parameters measured in a MultiMediaCard system assuming the recommended operating conditions (see "Chapter 10.2.3: Recommended operating conditions") and the temperature range as defined in "Chapter 10.1: Temperature characteristics"). The guaranteed power consumption does not include the current consumed by external units. Parameter Supply Current Supply Current Symbol I DD I DD Min Max 200 10 Unit uA mA Remark Standby state, Clock = 0Hz, V DD = 2.7V, VIH CMD,CLK = V DD Transfer state, Clock = 400kHz, V DD = 2.7V, VIH CMD,CLK = V DD VIL CMD,CLK = GND Transfer state, Clock = 5MHz, V DD = 2.7V, VIH CMD,CLK = V DD VIL CMD,CLK = GND Transfer state, Clock = 20MHz, V DD = 3.6V, VIH CMD,CLK = V DD VIL CMD,CLK = GND
Supply Current
I DD
25
mA
Supply Current
I DD
35
mA
Table 26: Guaranteed power consumption All operating characteristics are measured assuming the following load model for each output: The standard input capacity is C card =7pF. The standard bus capacitance is assumed to be C bus =30pF. The maximum number of cards which can be driven in a MultiMediaCard stack at full speed (20MHz) is 10. This leads to the following reference capacitance:
C L10 = n * C catd + C bus +10 * 7pF 30pF = 100pF
card output CL
Figure 19: Test circuit
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Parameter All Digital Inputs (Including I/O) Input Leakage Current All Outputs (push pull mode) High-Level Output Voltage Low-Level Output Voltage Low-Level Output Voltage (open drain mode) Command Input: CMD (Related to CLK) Input setup time Input hold time Outputs: CMD, DAT (Related to CLK) Output setup time Hold time
Symbol Min I LI V OH V OL V OL t ISU t IH t OSU t OH 0.75VDD
Max 10
Unit uA V V V ns ns ns ns
Remark 0V < VIN < VDD at I OHMIN at I OLMIN at I OLMIN S. Figure 20 S. Figure 20 S. Figure 20 S. Figure 20
0.125V DD 0.3V 3 3 5 5
Table 27. Operating characteristics At a reduced clock rate the card can drive a load of up to 30 cards:
C L30 = n * C catd + C bus = 30 * 7pF + 40pF = 250pF
With this load capacity the operating frequency is reduced to 5MHz.
tPP tWH tWL VIH
CLOCK
VIL tIH tHL tLH
VIH
Input
Valid
Valid VIL
tISU VOH
Output
Valid tOH tOSU
Valid VOL
Figure 20: Timing Diagram of Data Input and Output
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The access time (t AT ) is divided into two parts: * T SAD : The synchronous access time. This time defines the time of the maximum number of cycles which are required to access a byte of the memory field. * T AAD : The asynchronous access time to read a byte out of the memory field The synchronous part of the access time is seven cycles. At 20 MHz one cycle is 50 ns (1/f CLK ), multiplied with NSAD the resulting frame time is T SAD =15 ms. The asynchronous access delay of the MX53L03200 is T AAD =0.6 ms maximum. The resulting memory access time t AT is equal to the sum of both parts:
NSAD fCLK
tAT = tAAD + TSAD
with
TSAD =
tAT tSAD tAAD
CMD
command frame
response frame
DAT
data
Figure 21: Access Time
Parameter Synchronous access delay cycles Synchronous access delay Synchronous access delay Asynchronous access delay Memory access time Memory access time
Symbol N SAD T SAD T SAD T AAD t AT t AT
Max 300 60 15 0 60 15
Unit cycles us us us us us
Remark @5 MHZ clock frequency @20 MHZ clock frequency @5 MHZ clock frequency @20 MHZ clock frequency
Table 28: Access Time In the CSD are two fields to code the asynchronous and the synchronous access delay time: * TAAC, asynchronous access delay * NSAC, maximum number of cycles for receiving and interpreting of a command frame The value for the CSD field NSAC is calculated from NSAD (maximum: 300 cycles) by division with 100 and rounding up to the next integer: * NSAC=0x03(300 cycles) * TAAC=0x08(1ns) For more details on NSAC and TAAC CSD-entries see "Chapter 5.3: Card specific data (CSD)".
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9.3 Mechanical characteristics * MX53L03200 form factor: 24mm x 32mm x 1.4mm (WxLxH):
R0.2 MIN ALL AROUND
PAD SIDE
0.2 R0.2 MIN ALL AROUND 4.5 MIN 3 x R1.0 + 0.1 1.2MAX 1.65 + 0.4 0.1 M 7 6 5 6 x 2.5 =15.0 6.875 4 3 2 1 4.0 + 0.1 24.00 + 0.08 1.4 + 0.1
4.0 + 0.1 32.0 + 0.1
2 x R0.5 + 0.1
Figure 22: ROM MultiMediaCard shape Additional informations regarding mechanical topics, like connectors, environmental and testing parameters are part of a special document: [2].
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9.4 Label Dimension Each card has two sides : "marking" side (the side with 7 pins) shows the factory's manufacturing information; "label" side is an area where the label is stuck on the surface for the purpose of promotion and advertisement. Label size is defined as following :
4.0 + 0.1
20.3 REF.
4.0 + 0.1
32.0 + 0.1
R0.76 TYP
24.00 + 0.08
Label thickness: 0.076mm REF.
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10.Application notes
Additional application specific informations are available for the following topics: A guideline for MultiMediaCard integration into application: The MultiMediaCard Adapter[2]. This document describes also an generic VHDL model of the adapter.
11.References
[1] The MultiMediaCard, System Specification 1.4, MultiMediaCard Definition Group, March 1998 [2] The MultiMediaCard Adapter, Version 5.1, SIEMENS AG, June 1998
12.Number representations
* * * * * hexadecimal numbers: 0xAB, leading 0x, each digit represents 4 bits. binary numbers (single bit):"0". binary number (unsigned bit vector):"100100". 1k is equal to 1024. 1M is equal to 1k * 1k.
13.ORDER INFORMATION
Part No. MX53L03200LC-20 MX53L03200LC-50 Speed 200ns 50ns Frequency 5MHZ 20MHZ
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REVISION HISTORY
Revision No. Description 1.2 Voltage 2.7V 0x4(25mA) for VDD_R_CURR_MIN, 0x4(35mA) for VDD_R_CURR_MAX OCR value of 0x00FFE000 R3 frame contains value of 0x3F00FFE000FF Clock off <100uA, <200uA ; Low speed stby, tran<5mA; Initialization <5mA ; High speed data, tran <25mA, <35mA NSAC=0x03(300cycles) 1.3 Add Order Information Modify 9.2.4 Operating Characteristics:100-->200 1.4 Modify Figure 11: Data read timing (data transfer mode) 1.5 Modify Features Modify Table 21:Typical MX53L03200 supply current values Modify 9.2.4 Operating Characteristics:IDD=25mA, Clock=20-->5MHz Add data in Table 28:Access Time 1.6 Add 9.4 Label Dimension 1.7 Modify 5.1 Card identification (CID) 1.8 1. Added "Value" in Table 3: The CID fields 1.9 1. Changed Part No. from MX53L25600 to MX53L03200 2.0 1. Changed operating temperature from -20C to -25 C Page P1 P6 P15 P19 P28 P34 P36 P32 P23 P1 P28 P32 P34 P36 P5,6 P5 All P31 Date NOV/15/2000
JAN/12/2001 FEB/08/2001 MAR/02/2001
JUN/08/2001 JUL/04/2001 OCT/04/2001 MAY/06/2002 OCT/29/2002
P/N: PM0693
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REV. 2.0, OCT. 29, 2002
MX53L03200
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
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TEL:+81-44-246-9100 FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385 FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300 FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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